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By R. M. M. Oberman (auth.)

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Sample text

It contains a divide-by-8 counter and in cascade witli this by a mode signal M a programmable divide-by-31/32 counter. The output is designed in TTL circuitry. This is possible since the output shows a frequency fout ={l/248)fin or (I /256)fin. The adaptation of the counters in ECL technique to the outside TTL circuitry is performed in the 11 C83 package. M Q--~ Figure 2-31 Block diagram of prescaler llCS3 The cycle length of the cascaded counters is 248 or 256 steps. A division rate of 1/1000 can be obtained by a simple combination of prescaler l1 C83 with a binary counter as shown in figure 2-32.

With load = 1 and dear = 1 gates 11, 14, 17 and 20 are blocked with a 0 signal for the data inputs, and gates 10, 13, 16 and 19 are enabled for the ordinary counting operation of the circuit. Counters with J-K 07 T flip-flops The difference in operation between a D flip-flop and a J -K flip-flop (or T flip-flop) necessitates a difference in the circuitry of determining the cyde's end. In a BCD counter flip-flop W has to be reset to 0 on the tenth pulse of a cyde, and flip-flop Y has to be prevented from being set to 1.

The changes in the state of the counter under control of aseries of counting pulses aare gradually propagated through this counter. The flip-flops do not operate simultaneously on a c10ck pulse. This feature leads to difficulties in high-speed applications. ta Zo y Figure 24 Asynchronous binary counter BINARY COUNTERS 21 but that the next a pulse is going to be received and registered before the pulse generating process can be stopped. Counters of tbis type are usually called asynchronous counters, that is, not synchronously operating with all its flip-flops on the counting pulses.

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